Design high speed, high bandwidth, low power digital hardware solutions using SystemVerilog Take on the challenge of achieving the high performance goals of the product while minimizing power and area Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision Contribute to definition, micro-architecture and documentation of HW IP Collaborate closely with the Verification team to test and debug new HW IP Collaborate closely with the Verification team to close coverage on new HW IP Create assertion based models for functional and formal verification using SystemVerilog Create functional coverage models using SystemVerilog Evaluate synthesis results to verify the design meets the speed, power and area targets Support internal hardware integration SW teams around the world Support internal software teams during their application testing Collaborate with software teams to develop new features Use of various design tools (VCS Simulator, Synopsys Compiler , Linting, CDC, LEC, CLP etc.) to check and improve design quality Provide ideas and further the innovation of ASICs, IP cores, and process flows Strong problem solving and analytical thinking skills First-time-right hardware requires an attention to detail and careful planning Excellent communication skills Self-motivated, goal oriented, team player Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
