Verification of a complex IP block using UVM methodology Resolving architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision Collaborating closely with the Design team to test, debug and close coverage on the design Modifying testbench components such as scoreboard, agents, sequences, to verify new features Writing tests in SystemVerilog Writing functional coverage and assertions using SystemVerilog Regression maintenance and triaging of test failures Contributing to testbench architecture and optimization Contributing to testplan implementation and verification methodology Supporting integration testing of the design Performance testing Strong problem solving and analytical thinking skills Excellent communication skills Self-motivated, goal oriented, team player Experience with verification methodology (UVM, assertions, coverage-driven constrained-random verification) Experience with scripting languages (Python, CShell) Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
