Senior Pre-Silicon Verification Engineer
Intel View all jobs
- Toronto, ON
- Training
- Full-time
- Perform functional verification of digital and mixed-signal logic components including analog behavioral modeling and advanced verification techniques (UVM, real number modeling, AMS simulation).
- Create verification environments that accurately model analog-digital interactions and validate designs across process, voltage, and temperature (PVT) variations.
- Develop comprehensive IP verification plans, test benches, and scalable verification environments for mixed-signal microarchitecture specifications.
- Build verification frameworks supporting regression testing, continuous integration, and both digital and analog verification flows.
- Execute verification plans, analyze power/timing/performance metrics, and conduct system-level simulations and corner case analysis.
- Replicate, root cause, and debug complex issues in the pre-silicon environment, implementing corrective measures to resolve failing tests.
- Collaborate with digital and analog architects, RTL developers, and physical design teams to meet functional, performance, and power goals.
- Document test plans, drive technical reviews, and maintain/improve verification infrastructure and methodology while ensuring smooth pre-silicon to post-silicon correlation.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related field of study.
- 5+ years of experience in digital design verification or mixed-signal verification.
- 3+ years of experience with Pre-Silicon Verification environment architecture and development.
- Experience with complex mixed-signal IP verification or system-level verification.
- Experience in both digital verification methodologies (UVM/SystemVerilog).
- Perl, HTML, Python or similar scripting (Python preferred).
- Master's degree in Electrical Engineering, Computer Engineering, or in a STEM related field of study.
- Experience with working in mixed-signal design like SerDes or PLLs.
- Experience with SerDes PHY verification.
- Experience driving verification methodology changes and initiatives.
- Experience with Mixed Signal Verification (MSV).
- Experience with Gate Level Simulation (GLS).
- Experience with concepts of DFT, ATE, HVM.
- Competitive salary and comprehensive benefits package.
- Opportunity to work on Intel's most advanced mixed-signal designs and technologies.
- Access to cutting-edge mixed-signal verification tools and simulation infrastructure.
- Collaboration with world-class analog and digital design engineers and architects.
- Professional development opportunities in advanced mixed-signal verification techniques.
- Direct impact on Intel's leadership in mixed-signal semiconductor innovation.