
RTL Design Engineer
- Vancouver, BC
- Permanent
- Full-time
- Enjoys being in a collaborative environment where they can grow and learn with sense of pride.
- Strong analytical thinking and problem-solving skills with excellent attention to detail.
- Eager to learn new designs techniques and new protocols.
- Must have good communication and interpersonal skills.
- Microarchitectural design and RTL implementation of IP features.
- Participate in design specification and RTL code reviews.
- Collaborate with Design Verification team to execute on design features.
- Analyze RTL design for power and timing optimization.
- Improve the development flow targeting quality and efficiency using latest methodologies, including vendor tools and Artificial Intelligence.
- 3+ years of overall design experience in the ASIC industry.
- Familiar with industry standard high-speed protocols such as PCIe, CXL, SATA/SAS, USB.
- Knowledge in digital design and RTL implementation.
- Knowledge in synthesis and timing analysis to achieve timing closure.
- Experience in HDL (VHDL/Verilog), HVL (SystemVerilog) and SystemVerilog Assertions (SVA).
- Experience in design with multiple clock domains.
- Experience in low power design and methodology.
- Exposure to Makefile and other scripting languages like Perl, Python and Ruby.
- Experience with state-of-the-art industry standard Electronic Design Automation (EDA) Tools.
- BS (or higher) degree in Electronics/Electrical or Computer Engineering desired.
- Vancouver, BC, Canada or Markham, Ontario, Canada