Contribute to IP verification during the pre/post silicon phase of next generation SOC Collaborate with design and software teams to debug and resolve issues Design and translate high level customer use to hardware specific verification plans Develop and automate test plans; refactor and optimize test code Manage validation and testing of the driver/hardware Migrate/integrate cross team drivers to new platforms as test required Support post-silicon bring-up, functional, and performance testing Perform power correlations, analysis and reporting You will have a minimum of 1-5 years of experience Experience in Low Level software development in C, C++, Assembly and Python Experience with Windows and Linux OS environment Experience in ARM, DSP processors, Windows/Linux environments. Experience in automation and test/integration methodologies Experience developing/enhancing validation methodologies and infrastructure solutions Experience with SCM tools (Git, Perforce), and defect tracking (JIRA). Experience with digital and analog circuit is a strong asset Good communication skills (written and verbal) Strong debug skills Developing and optimizing test framework and tools to create a controlled validation environment to support large scale validation Designing and defining new validation strategy as well as detailed test plans Help debug efforts for issues found during Pre-silicon (FPGA) and Post-silicon Define, design, and execute platform Pre-Silicon and Post-Silicon validation plans for current and future products Debug hardware/software issues using Lauterbach Trace32 (T32) for register access, memory analysis, and automation. Experience with low-power modes, power/performance characterization, and correlation analysis. Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
