RTL Design Engineer
Rambus View all jobs
- Montreal, QC
- Permanent
- Full-time
- Follow latest developments in PCIe standards
- Micro-architecture and design of advanced PCIe and CXL IP, for PCIe7 and beyond
- Participate in FPGA prototyping and hardware validation
- Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation)
- Collaborate with a worldwide team
- Contribute to technical improvements on all aspects of the IP design domain
- Verilog and System Verilog
- Good English skills, communication skills, and willingness to work with an international team.
- Knowledge of UPF
- Knowledge of ASIC and FPGA design flow and tools (ASIC Synthesis, CDC / RDC / Linting, Quartus, Vivado)