Staff FPGA Design EngineerWe’re hiring a Staff FPGA Design Engineer to help combine deep chip design expertise with machine learning to build intelligent, end-to-end silicon design flows that move from research to production.What You’ll DoServe as FPGA/RTL domain expert for AI-driven chip design assistantsArchitect modern EDA workflows (spec to bitstream)Enable AI agents to generate correct-by-construction RTL, manage IP, and build processor-based systemsDevelop libraries, tools, datasets, and benchmarks to accelerate design velocityDefine strong verification standards and guide AI-generated UVM environmentsWhat You BringMaster’s in Electric Engineering, Computer Science or related field10–15 years of RTL design and/or verification experienceDeep expertise in Xilinx (Vivado/Vitis) and Intel/Altera (Quartus) ecosystemsStrong knowledge of AXI, PCIe, Ethernet, NoC, DDR5,SPI, I2CProficiency in SystemVerilog, Python, TCLClear communicator comfortable in a fast-paced AI startupBonusOpen-source contributions (Verilator, Cocotb, Yosys, OpenSTA)Experience across full chip flowExposure to ML or deep learningPast working experience for an AI startupScreening QuestionsHave you worked with Xilinx Vivado or Vitis for FPGA design?Have you worked with Intel/Altera Quartus for FPGA design?Do you have 10+ years of RTL design or verification experience?Have you led an FPGA project from specification to bitstream or production silicon?Have you designed or integrated high-speed interfaces such as AXI, PCIe, Ethernet, DDR5, SPI, I2C, or NoC?Have you used SystemVerilog for RTL design and/or verification?Have you built or guided UVM-based verification environments?Have you automated FPGA workflows using Python or TCL scripts?In a few lines, explain WHY YOU are an ideal fit for this Staff FPGA Design Engineer role.sasha@talenttohire.com