ASIC Physical Design, Sr Staff Engineer
Synopsys View all jobs
- Nepean, ON
- Training
- Full-time
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custom_fields.CareerAreas-ASIC-Physical-Design custom_fields.SubCategory-ASIC-Physical-Design custom_fields.EmployeeStatus-Employee custom_fields.unposting_date-2027-04-30 custom_fields.Multikeywordfacets-Hardware">Join our Talent Community! .Find Jobs ForWhere? Search JobsASIC Physical Design, Sr Staff Engineer - 16724Nepean, Ontario, CanadaEngineeringEmployeeSave Job ShareJump toOverviewOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.Play VideoJob DescriptionDate posted 04/07/2026Category Engineering Hire Type Employee Job ID 16724 Remote Eligible No Date Posted 04/07/2026We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are:You are an experienced ASIC Physical Design Engineer with a passion for innovation and a proven track record in complex SoC and test chip implementations. You thrive in collaborative environments, excel at cross-functional teamwork, and are ready to lead technical execution on advanced process nodes. Your expertise in the physical design flow and familiarity with industry-leading tools make you a valuable contributor to our mission of delivering robust, silicon-proven IP solutions.What You'll Be Doing:
- Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
- Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
- Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
- Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
- Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
- Driving tool flow automation and debugging to enhance productivity and design reliability.
- Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.
- Preparing and releasing all supporting views and documentation necessary for tape-out, maintaining mask tooling forms and checklists on foundry portals.
- Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
- Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
- Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
- Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
- Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
- Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.
- 9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
- Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
- Familiarity with IP integration, test chip methodology, and advanced verification flows.
- Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
- Experience coordinating complex, cross-functional projects and leading technical execution.
- Authorization to work in the USA.
- Analytical thinker with strong problem-solving skills and attention to detail.
- Effective communicator, able to articulate complex technical concepts to diverse stakeholders.
- Collaborative team player, fostering a culture of inclusion and innovation.
- Proactive leader, driving continuous improvement and embracing new technologies.
- Adaptable and resilient, thriving in fast-paced, dynamic environments.
- Committed to excellence and quality in every aspect of design and delivery.