
Analog Designer 2
- Markham, ON
- Temporary
- Full-time
- Construction of product I/O pad rings using established flows and scripts. Generated views include: Verilog, Def, Spice, and GDSII.
- Physical verification on designs that contain up to 200M devices including: LVS, DRC, ERC and PERC.
- Delivery of all needed waivers(Electronic Rule Check /Design Rule Check /EDRC/PERC) and documentation to SoC teams
- Facilitate ESD and design reviews for 3rd party IPs and I/O ring
- Tracking of IP versions, visual inspections and in-context XOR verifications.
- Strong understanding of physical verification checks (Layout VS Schematic /Design Rule Check /Electronic Rule Check/PERC), and ability to debug and resolve issues.
- Knowledge of chip level integration and Electrical Static Discharge /LUP concepts.
- Must have ability to communicate with various teams to articulate issues, requirements as they pertain to layout in order to facilitate solutions
- Physical verification experience using Mentor Calibre (Laoyt VS Schematic, Design Rule Check, PERC), and Synopsys tools (ICC/ICC2/ICV).
- Experience doing physical verification for tile of chip physical design would be an asset.
- Perl programming, TCL, SVRF, TVF programming not required, but would be advantages
- IP layout design experience and exposure to Cadence is a plus.
- Must be able to work independently and as part of a team
- Electrical/Computer/Biomedical/Mechanical Engineering Degree and/or Electronics related Diploma