Senior Staff Digital Design Engineer – Wireline PHYs

• Digital Design for PHYs: Architect, design, and implement RTL for key digital blocks used in PHYs, including adaptation engines, calibration logic, control/state machines, test features, DSP pipelines and DFT.
• Mixed-Signal Interface: Collaborate with analog/mixed-signal teams to define control interfaces, adaptation loops, and digital support for real-time calibration and equalization (e.g., DFE, CTLE, CDR support).
• Application Focus: Design PHY digital systems targeted for SerDes, Die-to-Die interfaces, and Parallel Optics, ensuring robust operation across voltage, temperature, and process corners.
• RTL Implementation & Verification: Develop synthesizable, lint-clean, CDC/RDC-aware RTL using Verilog/SystemVerilog. Collaborate with verification teams to ensure functional and coverage closure.
• Timing & Integration: Drive floorplan-aware and timing-closure-friendly design practices. Work closely with the physical design team to ensure optimal layout and integration of PHY IP into larger SoCs.
• Microcontroller Integration: Define and implement bus interfaces (e.g., APB, AHB, AXI) and register maps to enable seamless communication between PHY digital logic and embedded microcontrollers.
• Bring-up & Debug Support: Assist validation and post-silicon teams with lab bring-up, debug, and characterization of PHY behavior in hardware environments.
• Mentorship & Leadership: Provide technical leadership to junior engineers, participate in design reviews, and contribute to internal methodology and process improvements.

• Master’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of relevant experience, or PhD with 4+ years of relevant experience.
• Extensive experience in digital design, with a strong focus on high-speed PHY or SerDes development.
• Expertise in RTL design using Verilog/SystemVerilog, with deep knowledge of synthesis, timing closure, and CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) design techniques.
• Solid knowledge of DFT, BIST, and scan insertion for mixed-signal.
• Solid understanding of logic synthesis and static timing analysis (STA), including constraints development and timing closure at block and chip levels.
• Strong understanding of system-level design and integration with embedded microcontrollers, including bus protocols (e.g., APB, AHB, AXI), register map definition, firmware interfacing, and interrupt/event control.
• Experience developing control logic, DSP blocks, and adaptation/calibration systems for PHYs.
• Solid understanding of analog/digital co-design challenges in mixed-signal PHY development.
• Proficient with EDA tools for simulation, synthesis, lint, CDC/RDC analysis, and timing analysis.
• Familiar with scripting languages (e.g., Python, Perl, TCL) for design automation and flow customization.
• Strong problem-solving and debug skills, including post-silicon bring-up and lab correlation.

Marvell