Senior Staff Digital Design Engineer
Marvell View all jobs
- Ottawa, ON
- $118,700-158,300 per year
- Permanent
- Full-time
- Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
- Develop high speed data path and control plane RTL blocks using Verilog, synthesis and backend resources
- Integrate vendor IP and support
- Well versed with the complete ASIC flow from micro-architecture to customer deployment
- Post-silicon debug and correlation
- Develop ASIC specification and micro-architecture of signal processing and communications algorithms
- Assist in design automation of various aspects of the CAD EDA flow.
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
- 5+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology.
- Familiarity with the entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
- Experience with Verilog, System Verilog, Python, and Unix Shell.
- Experience in both RTL development (block and subsystem level) and gate level verification and debug.
- Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
- Effective communication and presentation skills and a team player