FPGA Engineer
- Ottawa, ON
- Permanent
- Full-time
- Develop and execute UVM-based testbenches in SystemVerilog for FPGA/ASIC verification.
- Initially focus on simulation tasks, with progression into design simulation and integration.
- Work across three FPGA generations: Gen 2 (currently missing features and test coverage; delivery due in 5 months), Gen 3 (design not yet started; expected to begin in the coming months), and Gen 1 (requires immediate support for UVM verification).
- Collaborate on designs involving multiple low-end Xilinx Artix-7 FPGAs per board, interfacing via PCIe, SPI, EPCs, and custom inter-FPGA links.
- Perform cross-domain logic analysis, including multi-clock domain verification.
- Conduct synthesis and post-synthesis analysis, including timing constraint development.
- Write comprehensive test plans, document test cases, and maintain high-quality documentation.
- Ramp up quickly in a fast-paced environment with limited existing documentation.
- Strong experience in FPGA/ASIC verification using UVM and SystemVerilog.
- Experience in digital design and understanding of FPGA architecture.
- Familiarity with multi-clock domain logic, cross-domain synchronization, and timing closure.
- Ability to define and analyze timing constraints and perform post-synthesis validation.
- Excellent documentation and communication skills.
- Experience with Perl scripting for automation and test development.
- Familiarity with PCIe, AXI, and external memory interfaces.
- Ability to work independently and adapt to evolving project needs.