ASIC Digital Design, Staff Engineer

• Define verification plans and build verification environments for IP level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification to achieve functional safety metrics (including ISO26262 compliance) for automotive applications
• Write test cases, checkers, and coverage that implement the verification test plan.
• Provide technical leadership to junior engineers and interns

• Bachelors or Masters with 5+ years of digital verification experience in the industry
• RTL verification using coverage driven verification techniques
• Scripting in any language such as Python, Perl
• Proficient in HDL languages System Verilog, Verilog, or VHDL
• Good analytical, oral, and written communication skills
• Self-motivated, proactive team player

• To grow and manage verification of product end-to-end.
• Mixed-signal verification methodology.
• Cross-functional learning and interaction with professional teams across domains and geographies.
• Customer-facing role working in close collaboration with pre and post-sales team
• Develop systematic ways to address new problems, think outside of the box
• Have an impact on the new product architectures, quality and development strategies

Synopsys